Real-Time Performance
Deterministic Logging for Hybrid FPGA Soft Cores
Timestamping approach when soft CPUs share BRAM with DSP pipelines for imaging probes.
₩15,200,000 · 3 weeks
Overview
Explains how to keep logs monotonic without starving imaging DMA, including lightweight ring buffer hashing for tamper-evident exports.
What is inside
- BRAM arbitration sketches
- Timestamp monotonicity proof outline
- Log export hashing recipe
- Vendor UART FIFO depth commentary
- Soft reset sequencing for partial reconfiguration
- Debug header pinout suggestion
- Peer review checklist for log schema changes
Outcomes
- Fewer “ghost events” in exported traces
- Better alignment between FPGA and firmware sign-off owners
- Cleaner story for auditors reviewing log integrity
Responsible editor
Haneul Park
Embedded lead with a decade on signal chains for wearable and bedside monitors.
FAQ
Examples use vendor-neutral pseudocode; toolchain-specific scripts are not included.
Field notes
The BRAM arbitration sketch finally matched what our FPGA contractor drew verbally.