Bench Notes: When SPI Flash Looks Fast But Boot Feels Slow

We keep seeing teams ship impressive SPI clock numbers while boot still misses internal milestones. The gap is rarely the raw MHz—it is how instruction fetches interact with cache line fills once code grows past a tidy demo.

In one Seoul lab we paired a simple GPIO toggle sweep with a spreadsheet that ties each boot stage to a physical artifact. Reviewers stopped asking for “another week of tuning” and started asking which artifact was missing.

A third paragraph is reserved for limitations: this note does not cover external OS loaders or hypervisor handoffs. Those deserve their own brief because the evidence pack looks different.

Finally, we document how to archive the spreadsheet alongside binaries so a year-later auditor can still reproduce the narrative without calling the original author on vacation.